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11-6
Hot-Socketing Implementation
SV51013
2013.05.06
Related Information
? Power-Up Sequence on page 11-7
? Stratix V Device Datasheet
Provides details about the Stratix V hot-socketing specifications.
Hot-Socketing Implementation
The hot-socketing feature tri-state the output buffer during power up and power down of the power supplies.
When these power supplies are below the threshold voltage, the hot-socketing circuitry generates an internal
HOTSCKT signal.
Hot-socketing circuitry prevents excess I/O leakage during power up. When the voltage ramps up very
slowly, I/O leakage is still relatively low, even after the release of the POR signal and configuration is complete.
Note: The output buffer cannot flip from the state set by the hot-socketing circuitry at very low voltage.
To allow the CONF_DONE and nSTATUS pins to operate during configuration, the hot-socketing feature
is not applied to these configuration pins. Therefore, these pins will drive out during power up and
power down.
Figure 11-3: Hot-Socketing Circuitry for Stratix V Devices
Power-On
Reset (POR)
V CCIO
Monitor
Weak
Pull-Up
Resistor
R
Output Enable
PAD
Voltage
Hot-Socket
Tolerance
Control
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuitry monitors the voltage level of the power supplies and keeps the I/O pins tri-stated until
the device is in user mode. The weak pull-up resistor (R) in the Stratix V input/output element (IOE) is
enabled during configuration download to keep the I/O pins from floating.
The 3.0-V tolerance control circuit allows the I/O pins to be driven by 3.0 V before the power supplies are
powered and prevents the I/O pins from driving out before the device enters user mode.
Note: For the V CC_AUX power supply, POR only monitors one of the VCC_AUX pins. You must connect all
the VCC_AUX pins.
Altera Corporation
Power Management in Stratix V Devices
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